1. Field of the Invention
The invention generally relates to nanoelectronic devices. More particularly, the invention relates to nanoelectronic devices that include carbon nanotubes.
2. Description of the Relevant Art
Silicon based CMOS technology scaling has driven the semiconductor industry towards cost minimization and performance improvement in the past four decades, and is rapidly approaching its end. On the other hand, nanotechnology has achieved significant progress in recent years, fabricating a variety of nanometer scale devices, e.g., molecular diodes and carbon nanotube field effect transistors. This has provided new opportunities for VLSI circuits to achieve continuing cost minimization and performance improvement in a post-silicon-based-CMOS-technology era.
However, significant challenges need to be overcome before reliable high performance nanoelectronic circuits can be achieved. Challenges that need to be overcome include:                1. Manufacturability. As minimum layout feature size is becoming smaller than lithography light wavelength, traditional lithography based manufacturing process can no longer achieve the needed resolution, leading to significant process variation. Resolution enhancement and other design for manufacturability techniques become less applicable as scaling continues. Alternatively, nanoelectronic circuits are expected to be based on bottom-up self-assembly based manufacturing processes, e.g., molecular beam epitaxy (MBE). Such bottom-up self-assembly manufacturing processes provide regular structures, e.g., perfectly aligned carbon nanotubes. Consequently, nanoelectronic circuits need to rely on reconfigurability to achieve functionality and reliability.        2. Reliability. Technology scaling has led to increasingly significant process and system runtime variations, including critical dimension variation, dopant fluctuation, electromagnetic emission, alpha particle radiation and cosmos ray strikes. Such variations cannot be avoided by manufacturing process improvement, and is inherent at nanometer scale, as is dictated by the stochastic nature of quantum physics. A variety of robust design techniques, including redundant, adaptive, and resilient design techniques at multiple (architecture, circuit, layout) levels, are needed to achieve a reliable nanoelectronic circuit.        3. Performance. Nanoscale devices have achieved high performance in the absence of significant load, however, system performance bottleneck lies in global interconnects. Rent's rule predicts that the maximum global interconnect wirelength scales with the gate number in a circuit in a power law. Interconnect design would be critical to performance improvement of large scale nanoelectronic circuits.        
Existing nanoelectronic architectures are in three categories: (1) resonant tunneling diodes and negative differential resistors based on early nanoelectronic architecture, (2) mainstream hybrid nano-CMOS technology based nanoelectronic architecture, and (3) fax future DNA-guided self-assembly based nanoelectronic architecture.
Carbon nanotubes and carbon nanotube field effect transistors are expected to be the building blocks of nanoelectronic circuits due to their extraordinary properties. Carbon nanotube crossbar structure is one of the most prominent candidates for nanoelectronic design platform. Recently, UIUC researchers have achieved fabrication of dense perfectly aligned carbon nanotube arrays. Such a carbon nanotube crossbar structure forms the basis of nanoscale memories, and provides a reconfigurable computing platform of manufacturability and reliability for next generation VLSI designs.
However, no nanoelectronic architecture has been proposed which is solely based on carbon nanotubes and carbon nanotube field effect transistors. The reasons include lack of a self-assembly process which could form complex carbon nanotube structures, or, absence of a reconfigurable carbon nanotube device which could provide functionality and reliability.
Another outstanding challenge for realizing such nanoelectronic systems is how to precisely address an individual nanoscale wire (e.g., carbon nanotube) in an array. Designing a nano-addressing circuit is a challenging task, because (1) the nanoscale layout cannot be manufactured precisely unless it is of a regular structure, and (2) the nano-addressing circuit cannot be based on reconfigurability since it provides reconfigurability to the rest of the nanoelectronic system. Existing nano-addressing circuits require precise layout control such as lithography, doping, or etching, which is highly unlike to achieve alignment at the nanometer scale due to the presence of prevalent defects and significant process variations. These techniques also exhibit certain levels of randomness, which brings nanoscale wires that cannot be differentiated or addressed, and requires testing schemes which associate nanoscale wires with addresses.
Among various nanotechnology devices, carbon nanotube field effect transistors are the most promising candidates to replace the current CMOS field effect transistors as the building blocks of nanoelectronic circuits. Carbon nanotubes are one of the most promising candidates for interconnect technology at nanometer scale, due to their extraordinary properties in electrical and thermal conductivity, and mechanical strength. A carbon nanotube (“CNT”) is a one-atom-thick graphene sheet rolled up in a cylinder having a nanometer order diameter, which is semiconductive or metallic depending on its chirality. The cylinder form eliminates boundaries and boundary-induced scattering, yielding electron mean free path on the order of micrometers compared with few tens of nanometers in copper interconnects. This gives extraordinary current carrying capacity, achieving a current density on the order of 109 A/cm2. However, large resistance exists at CNT-metal contacts, reducing the performance advantage of CNTs over copper interconnects.
Three kinds of carbon nanotube based field effect transistors (CNFETs) have been manufactured:                (1) A Schottky barrier based carbon nanotube field effect transistor (SB-CNFET) consists of a metal-nanotube-metal junction, and works on the principle of direct tunneling through the Schottky barrier formed by direct contact of metal and semiconducting nanotube. The barrier width is modulated by the gate voltage. This device has the most mature manufacturing technique up to today, while two problems limit its future: (a) The metal-nanotube contact severely limits current. (b) The ambipolar conduction means this device cannot be applied to conventional circuit design methods.        (2) A MOSFET-like CNFET is made by doping a continuous nanotube on both sides of the gate, thus forming the source/drain regions. This is a unipolar device of high on-current.        (3) A band-to-band tunneling carbon nanotube field effect transistor (T-CNFET) is made by doping the source and the drain regions into p+ and n+ respectively. This device has low on-current and ultra low off current, making it potential for ultra low power applications.        
Molecular electronic devices are based on two families of molecules: the catenanes which consist of two or more interlocked rings, and the rotaxanes which consist of one or more rings encircling a dumbbell-shaped component. These molecules can be switched between states of different conductivities in a redox (reduction/oxidation) process by applying currents through them, providing reconfigurability for nanoscale devices.
A variety of reconfigurable nanoscale devices have been proposed. Resonant tunneling diodes based on redox active molecules are configurable on/off. Nanowire field effect transistors with redox active molecules at gates are of high/low conductance. Spin-RAM devices are of high/low conductivity based on the parallel/anti-parallel magnetization configuration of the device which is configured by the polarity of the source voltage. A double gate Schottky barrier CNFET is configurable to be a p-type FET, an n-type FET, or off, by the electrical potential of the back gate. A double gate field effect transistor with the back gate driven by a three state RTD memory cell is configurable to be a transistor or an interconnect, reducing reconfiguration cost of a gate array.
At least three categories of nanoelectronic architectures have been proposed. An early nanoelectronic architecture, NanoFabrics, was based on molecular resonant tunneling diodes (RTDs) and negative differential resistors (NDRs). It was observed that passive device (diode/resistor) based circuits lack signal gain to recover from signal attenuation, while combining with CMOS circuits compromises scaling advantages. Latches based on negative differential resistors (NDRs) were proposed, which, unfortunately, have become obsolete since the publication.
The majority of the existing nanoelectronic architectures are based on a hybrid nano-CMOS technology, with CMOS circuits complementing nanoelectronic circuits. In FPNI (CMOL), a nanowire crossbar is placed on top of CMOS logic gates (inverters). The nanowires provide programmable interconnects (and wired-OR logic), while the CMOS gates(inverters) provide logic implementation (signal inversion and gain). Such architectures achieve compromised scaling advantage in term of device density. It has been proposed to combine programmable nanoscale diode logic arrays with fixed simple CMOS circuitry, e.g., of precharge and evaluation transistors as in domino logic for signal gain. Sequential elements need also to be implemented as CMOS circuits. However, the optimal size of a combinational logic block is typically small (e.g., of 30-50 gates), which results in significant CMOS circuitry overhead in such architectures. An exception is memory design, where CMOS technology provides peripheral circuitry such as address decoders and read sensors with moderate overhead, while nanotechnology provides scaling advantage in memory cells.
The third category of existing nanoelectronic architectures relies on DNA-guided self-assembly to form 2-D scuffles for nanotubes or 3-D DNA-rods. Such technologies target application in the far future.
A nano-addressing circuit consists of a crossbar of orthogonal microscale wires and nanoscale wires. Electrical signals (address signals) coming from the microscale wires (address lines) supposedly select one of the nanoscale wires (data lines) to be conductive (for data in/out). Existing nano-addressing circuits are realized as binary decoders, i.e., every nanoscale wire is selected by a (supposedly unique) binary address. This requires that each nanoscale wire needs to have a unique gate configuration. However, such precise layout design is unlikely to achieve at a sublithographic nanometer scale (without significantly compromised yield), because nanoscale structures are expected to be bottom-up self-assembled regular structures, instead of defined by a top-down process like lithography.
Existing nano-addressing mechanisms are in four categories as follow.                1. Randomized contact decoder includes gold particles which are deposited at random as contacts between nanoscale and microscale wires. Testing and feedback provide a one-to-one mapping between a nanoscale wire and an address.        2. Undifferentiated nanoscale wires are addressable by microscale wires with (e.g., lithography defined) different gate configurations (which requires nanoscale wire spacing in the same order of lithography resolution).        3. Alternatively, different gate configurations are realized in the nanoscale wires, by growing lightly-doped and heavily-doped carbon nanotubes of different length alternatively, while the microscale wires are undifferentiated. A microscale wire crossing a lightly-doped nanotube segment forms a gate, while a heavily-doped nanotube segment is always conductive for all possible signals in the microscale wire. In such a case, precise control of the lengths of the lightly- and heavily-doped nanotube segments would be critical.        4. In radial addressing, multi-walled carbon nanotubes are grown with lightly- and heavily-doped shells, an etching process removes the heavily-doped outer shells at precise locations, and defines the gate configurations at each crossing of nanoscale and microscale wires.        
Process variations are inevitably significant at nanometer scale due to the stochasticness of quantum physics and thermodynamics. As a result, these existing nano-addressing structures have limited yield, e.g., there is certain probability that two nanoscale wires have identical or similar gate configuration due to process variation. Furthermore, nanoscale wires are mostly partially selected, e.g., they may not achieve the ideal conductivity upon selected, due to process variations such as misalignment, dopant variation, etc.